figure 1. ads-932 functional block diagram 3-state output register 29 bit 1 (msb) 28 bit 1 (msb) 27 bit 2 26 bit 3 25 bit 4 24 bit 5 23 bit 6 22 bit 7 21 bit 8 20 bit 9 19 bit 10 18 bit 11 17 bit 12 16 bit 13 15 bit 14 14 bit 15 13 bit 16 (lsb) timing and control logic gain adjust 6 +3.2v ref. out 1 offset adjust 5 eoc 32 analog ground 4, 36 digital ground 7, 30 +5v digital supply 31 C5v supply 37 +5v analog supply 38 no connection 39, 40 custom gate array power and grounding 2-pass analog-to-digital converter s/h gain adjust ckt. offset adjust ckt. precision +3.2v reference analog input 3 start convert 12 comp. bits 35 10 fstat1 11 fstat2 8 fifo/dir 9 fifo/read 34 output enabl e 33 overflow block diagram the low-cost ads-932 is a 16-bit, 2mhz sampling a/d converter. this device accurately samples full-scale input signals up to nyquist frequencies with no missing codes. the dynamic performance of the ads-932 has been optimized to achieve a signal-to-noise ratio (snr) of 87db and a total harmonic distortion (thd) of C88db. packaged in a 40-pin tdip, the functionally complete ads-932 contains a fast-settling sample-hold ampli? er, a subranging (two-pass) a/d converter, an internal reference, timing/control logic, and error-correction circuitry. digital input and output levels are ttl. the ads-932 only requires the rising edge of the start convert pulse to operate. requiring only 5v supplies, the ads-932 dissipates 1.85 watts. the device is offered with a bipolar (2.75v) analog input range or a unipolar (0 to C5.5v) input range. models are available for use in either commercial (0 to +70c) or military (C55 to +125c) operating tempera- ture ranges. a proprietary, auto-calibrating, error-cor- recting circuit enables the device to achieve speci? ed performance over the full hi-rel temperature range. typical applications include medical imaging, radar, sonar, communications and instrumentation. product overview input/output connections pin function pin function 1 +3.2v ref. out 40 no connection 2 unipolar 39 no connection 3 analog input 38 +5v analog supply 4 analog ground 37 C5v supply 5 offset adjust 36 analog ground 6 gain adjust 35 comp. bits 7 digital ground 34 output enable 8 fifo/dir 33 overflow 9 fifo read 32 eoc 10 fstat1 31 +5v digital supply 11 fstat2 30 digital ground 12 start convert 29 bit 1 (msb) 13 bit 16 (lsb) 28 bit 1 (msb) 14 bit 15 27 bit 2 15 bit 14 26 bit 3 16 bit 13 25 bit 4 17 bit 12 24 bit 5 18 bit 11 23 bit 6 19 bit 10 22 bit 7 20 bit 9 21 bit 8 features 16-bit resolution 2mhz sampling rate functionally complete no missing codes over full hi-rel temperature range edge-triggered 5v supplies, 1.85 watts small, 40-pin, ceramic tdip 87db snr, C88db thd ideal for both time and frequency-domain applications ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 1 of 9
physical/environmental parameters min. typ. max. units operating temp. range, case ADS-932MC 0 +70 c ads-932mm C55 +125 c thermal impedance jc 4 c/watt ca 18 c/watt storage temperature range C65 +150 c package type 40-pin, metal-sealed, ceramic tdip weight 0.56 ounces (16 grams) absolute maximum ratings parameters limits units +5v supply (pins 31, 38) 0 to +6 volts C5v supply (pin 37) 0 to C6 volts digital inputs (pin 8, 9, 12, 34, 35) C0.3 to +v dd +0.3 volts analog input (pin 3) bipolar 2.7 5 volts unipolar 0 to -5.5 volts lead temperature (10 seconds) +300 c +25c 0 to +70c C55 to +125c analog inputs min. typ. max. min. typ. max. min. typ. max. units input voltage range unipolar 0 to C5.5 0 to C5.5 0 to C5.5 volts bipolar 2.75 2.75 2.75 volts input resistance (pin 3) 655 687 685 685 input resistance (pin 2) 418 426 400 400 input capacitance 10 15 10 15 10 15 pf digital inputs logic levels logic "1" +2.0 +2.0 +2.0 volts logic "0" +0.8 +0.8 +0.8 volts logic loading "1" +20 +20 +20 a logic loading "0" ? C20 C20 C20 a start convert positive pulse width ? 40 250 40 250 40 250 ns static performance resolution 16 16 16 bits integral nonlinearity 1.0 1.5 2.0 lsb differential nonlinearity (f in = 10khz) C0.95 0.5 +1.0 C0.95 0.5 +1.0 C0.95 0.5 +1.5 lsb full scale absolute accuracy 0.1 0.3 0.15 0.5 0.5 0.8 %fsr bipolar zero error (tech note 2) 0.1 0.2 0.2 0.4 0.5 0.9 %fsr bipolar offset error (tech note 2) 0.1 0.3 0.2 0.5 0.4 0.9 %fsr gain error (tech note 2) 0.1 0.3 0.15 0.5 0.5 0.9 %fsr no missing codes (f in = 10khz) 16 16 16 bits dynamic performance peak harmonics (C0.5db) dc to 500khz C90 C81 C90 C81 C88 C80 db 500khz to 1mhz C90 C81 C90 C81 C88 C74 db total harmonic distortion (C0.5db) dc to 500khz C88 C80 C88 C80 C85 C78 db 500khz to 1mhz C87 C80 C87 C80 C84 C73 db signalCtoCnoise ratio (w/o distortion, C0.5db) dc to 500khz 83 87 83 87 80 85 db 500khz to 1mhz 82 86 82 86 80 84 db signal-to-noise ratio ? (& distortion, C0.5db) dc to 500khz 79 84 79 84 76 82 db 500khz to 1mhz 78 84 78 84 73 82 db two-tone intermodulation distortion (f in = 200khz, 240khz, f s = 2mhz, C0.5db) C89 C89 C89 db noise 83 83 83 vrms input bandwidth (C3db) small signal (C20db input) 7.8 7.8 7.8 mhz large signal (C0.5db input) 7.1 7.1 7.1 mhz feedthrough rejection (f in = 1mhz) 90 90 90 db slew rate 77 77 77 v/s aperture delay time +8 +8 +8 ns aperture uncertainty 5 5 5 ps rms s/h acquisition time (to 0.001%fsr, 5.5v step) 200 225 200 225 200 225 ns overvoltage recovery time ? 250 500 250 500 250 500 ns a/d conversion rate 2 2 2 mhz functional specifications (t a = +25c, v cc = -5v +v dd = +5v, 2mhz sampling rate, and a minimum 3 minute warmup ? unless otherwise speci? ed.) ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 2 of 9
technical notes +25c 0 to +70c C55 to +125c analog output min. typ. max. min. typ. max. min. typ. max. units internal reference voltage 3.15 +3.2 3.25 3.15 +3.2 3.25 3.15 +3.2 3.25 volts drift 30 30 30 ppm/c external current 5 5 5 ma digital outputs logic levels logic "1" +2.4 +2.4 +2.4 volts logic "0" +0.4 +0.4 +0.4 volts logic loading "1" C4 C4 C4 ma logic loading "0" +4 +4 +4 ma delay, falling edge of enable to output data valid 20 20 20 ns output coding straight binary, complementary binary, complementary offset binary, complementary two's complement, offset binary, two's comple ment power requirements power supply ranges ? +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 volts C5v supply C4.75 C5.0 C5.25 C4.75 C5.0 C5.25 C4.9 C5.0 C5.25 volts power supply currents +5v supply +225 260 +225 260 +225 260 ma C5v supply C140 C135 C140 C135 C140 C135 ma power dissipation 1.85 2.0 1.85 2.0 1.85 2.0 watts power supply rejection 0.07 0.07 0.07 %fsr/%v footnotes: ? all power supplies must be on before applying a start convert pulse. all supplies and the clock (start convert) must be present during warmup periods. the device must be continuously converting during this time. there is a slight degradation in performance when operating the device in the unipolar mode. ? when comp. bits (pin 35) is low, logic loading "0" will be C350a. ? a 2mhz clock with a positive pulse width is used for all production testing. see timing diagram for more details. 40ns < start pulse < 175ns or 280ns < start pulse < 460ns (snr + distortion) C 1.76 + 20 log full scale amplitude actual input amplitude 6.02 ? effective bits is equal to: ? this is the time required before the a/d output data is valid once the analog input is back within the speci? ed range. this time is only guaranteed if the input does not exceed 4.75v (bipolar) or +2 to C7.5v (unipolar). ? the minimum supply voltages of +4.9v and C4.9v for vdd are required for C55c operation only. the minimum limits are +4.75v and C4.75v when operating at +125c. 1. obtaining fully speci? ed performance from the ads-932 requires care- ful attention to pc-card layout and power supply decoupling. the device's analog and digital ground systems are connected to each other internally. for optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. bypass all power supplies and the +3.2v reference output to ground with 4.7f tantalum capacitors in parallel with 0.1f ceramic capacitors. locate the bypass capacitors as close to the unit as possible. 2. the ads-932 achieves its speci? ed accuracies without the need for exter- nal calibration. if required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in figure 2. when using this circuitry, or any similar offset and gain calibration hard- ware, make adjustments following warmup. to avoid interaction, always adjust offset before gain. tie pins 5 and 6 to analog ground (pin 4) if not using offset and gain adjust circuits. 3. pin 35 (comp. bits ) is used to select the digital output coding format of the ads-932 (see tables 2a and 2b). when this pin has a ttl logic "0" applied, it complements all of the ads-932's b1-b16 & b1outputs. pin 35 is ttl compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. there is an internal pull-up resistor on pin 35 allowing it to be either connected to +5v or left open when a logic "1" is required. 4. to enable the three-state outputs, connect output enable (pin 34) to a logic "0" (low). to disable, connect pin 34 to a logic "1" (high). 5. applying a start convert pulse while a conversion is in progress (eoc = logic "1") will initiate a new and probably inaccurate conversion cycle. data from both the interrupted and subsequent conversions will be invalid. 6. do not enable/disable or complement the output bits or read from the fifo during the conversion process (from the rising edge of eoc to the falling edge of eoc ). 7. the overflow bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1s or when the input equals or exceeds the voltage that produces all 0s. when comp bits is activated, the above conditions are reversed. 8. when con? guring the ads-932 for the unipolar mode, pin 1 (+3.2v ref.) should be connected to pin 2 (unipolar) through a non-inverting op-amp. for precision dc applications an op- 07 type ampli? er is recommended, while ac applications requiring the lowest level of harmonic distortion should consider the ad9631. when con? guring the ads-932 for the bipolar mode, pin 2 (unipolar) should be physically disconnected from the surrounding circuitry. this will help prevent noise from coupling into the a/d. ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 3 of 9
internal fifo operation the ads-932 contains an internal, user-initiated, 18-bit, 16-word fifo memory. each word in the fifo contains the 16 data bits as well as the msb and overflow bits. pins 23 (fifo/dir ) and 10 (fifo read) control the fifo's operation. the fifo's status can be monitored by reading pins 10 (fstat1) and 11 (fstat2). when pin 8 (fifo/dir ) has a logic "1" applied, the fifo is inserted into the digital data path. when pin 8 has a logic "0" applied, the fifo is transpar- ent, and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (enable ). read and write commands to the fifo are ignored when the ads-932 is operated in the "direct" mode. it takes a maximum of 20ns to switch the fifo in or out of the ads-932's digital data path. fifo write and read modes once the fifo has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of fifo read (pin 9). assuming the fifo is initially empty, it will accept data (18-bit words) from the next 16 consecu- tive a/d conversions. as a precaution, pin 9 (which controls the fifo's read function) should not be low when data is ? rst written to an empty fifo. when the fifo is initially empty, digital data from the ? rst conversion (the "oldest" data) appears at the output of the fifo immediately after the ? rst conversion has been completed and remains there until the fifo is read. if the output three-state register has been enabled (logic "0" applied to pin 34), data from the ? rst conversion will appear at the output of the ads-932. attempting to write a 17th word to a full fifo will result in that data, and any subsequent conversion data, being lost. once the fifo is full (indicated by fstat1 and fstat2 both equal to "1"), it can be read by dropping the fifo read line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. since the ? rst data word is already present at the fifo output, the ? rst read command (the ? rst rising edge applied to fifo read) will bring data from the second conversion to the output. each subsequent read command/rising edge brings the next word to the output lines. after the 15th rising edge brings the 16th data word to the fifo output, the subsequent falling edge on read will update the status outputs (after a 20ns maximum delay) to fstat1 = 0, fstat2 = 1 indicating that the fifo is empty. if a read command is issued after the fifo empties, the last word (the 16th conversion) will remain present at the outputs. fifo reset feature at any time, the fifo can be reset to an empty state by putting the ads-932 into its "direct" mode (logic "0" applied to pin 8, fifo/dir ) and also applying a logic "0" to the fifo read line (pin 9). the empty status of the fifo will be indicated by fstat1 going to a "0" and fstat2 going to a "1". the status outputs change 40ns after applying the control signals. fifo status, fstat1 and fstat2 monitor the status of the data in the fifo by reading the two status pins, fstat1 (pin 10) and fstat2 (pin 11). contents fstat1 fstat2 empty (0 words) 0 1 calibration procedure connect the converter per figure 2. any offset/gain calibration procedures should not be implemented until the device is fully warmed up. to avoid interaction, adjust offset before gain. the ranges of adjustment for the circuits in figure 2 are guaranteed to compensate for the ads-932s initial accuracy errors and may not be able to compensate for additional system errors. a/d converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. this is accomplished by connecting led's to the digital outputs and performing adjustments until certain led's "? icker" equally between on and off. other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. for the ads-932, offset adjusting is normally accomplished when the ana- log input is 0 minus ? lsb (C42v). see table 2b for the proper bipolar output coding. gain adjusting is accomplished when the analog input is at nominal full scale minus 1? lsb's (+2.749874v). note: connect pin 5 to analog ground (pin 4) for operation without zero/offset adjustment. connect pin 6 to pin 4 for operation without gain adjustment. zero/offset adjust procedure 1. apply a train of pulses to the start convert input (pin 12) so that the converter is continuously converting. 2. for unipolar or bipolar zero/offset adjust, apply C42v to the analog input (pin 3). 3. for bipolar inputs, adjust the offset potentiometer until the code ? ickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). for unipo- lar inputs, adjust the offset potentiometers until all output bits are 0's and the lsb ? ickers between 0 and 1 with pin 35 tied high (straight binary) or until all bits are 1's and the lsb ? ickers between 0 and 1 with pin 35 tied low (complementary binary). 4. two's complement coding requires using bit 1 (msb ) (pin 29). with pin 35 tied low, adjust the trimpot until the output code ? ickers between all 0s and all 1s. gain adjust procedure 1. apply +2.749874v to the analog input (pin 3). 2. for bipolar inputs, adjust the gain potentiometer until all output bits are 0s and the lsb ? ickers between a 1 and 0 with pin 35 tied high (comple- mentary offset binary) or until all output bits are 1s and the lsb ? ickers between a 1 and 0 with pin 35 tied low (offset binary). 3. two's complement coding requires using bit 1 (msb ) (pin 29). with pin 35 tied low, adjust the gain trimpot until the output code ? ickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110. table 2a. setting output coding selection (pin 35) output format pin 35 logic level complementary offset binary 1 offset binary 0 complementary twos complement (using msb , pin 29) 1 twos complement (using msb , pin 29) 0 straight binary 1 complementary binary 0 figure 2. bipolar connection diagram ads-932 20k 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 overflow eoc bit 1 (msb) bit 1 (msb) bit2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 (lsb) analog ground digital ground 0.1f 4.7f 0.1f comp. bits 4.7f +3.2v ref. out fifo read 31 7, 30 35 1 9 +5v digital C5v +5v offset adjust gain adjust 5 6 3 0.1f 4.7f 4, 36 37 0.1f 4.7f 38 ++ 20k C5v +5v C5v +5v analog 12 start convert analog input 34 enable 8 fifo/dir 10 fstat1 11 fstat2 +5v +5v +5v C5v unipolar c onnect for unipolar mode 2 6.8f ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 5 of 9
thermal requirements all datel sampling a/d converters are fully characterized and speci? ed over operating temperature (case) ranges of 0 to +70c and C55 to +125c. all room-temperature (t a = +25c) production testing is performed without the use of heat sinks or forced-air cooling. thermal impedance ? gures for each device are listed in their respective speci? cation tables. these devices do not normally require heat sinks, however, standard precau- tionary design and layout procedures should be used to ensure devices do not overheat. the ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. electrically insulating, thermally conductive "pads" may be installed underneath the package. devices should be soldered to boards rather than "socketed", and of course, minimal air ? ow over the surface can greatly help reduce the package temperature. figure 3. ads-932 timing diagram this device has three pipeline delays. four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the a/d. start convert internal s/h nn+1 acquisition time 225ns typ. 20ns typ. eoc 75ns typ. output data data n-4 valid data n-2 valid invalid data data n-3 valid 20ns typ. n+2 data n-1 valid 440ns typ. 60ns typ. invalid data notes: 100ns typ. n+3 275ns typ. 45ns typ. 260ns typ. conversion time hold the start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec (when sampling at 2mhz) to ensure proper operation. for sampling rates lower than 2mhz, the start pulse can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. a 2mhz clock with a 100nsec p ositive p ulse width is used for all p roduction testin g . scale is approximately 50ns per division. fs = 2mhz. 1. 2. 3. figure 4. fft analysis of ads-932 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 C130 C140 C150 C160 C170 0 100 200 300 400 500 600 700 800 900 1000 frequency (khz) ( fs = 2mhz, fin = 975khz, vin = C0.5db, 16,384- p oint fft ) amplitude relative to full scale (db) ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 6 of 9
figure 5. ads-932 evaluation board schematic 20k r4 1 2 3 u2 9 8 7 6 5 4 3 2 11 1 19 18 17 16 15 14 13 12 0 20 1 74hct573 uut b6 b7 b8 b9 b10 b11 +5vd dgnd msb b2 b3 b4 b5 b12 b13 b14 b15 lsb start fstat2 fstat1 nc nc +5va -5va agnd comp enable of eoc read fifo/dir dgnd gain offset agnd ana in +3.2vref u6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 u1 12 11 13 8 9 10 74hct74 2.2f c13 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 p1 fst2 start fst1 b16 fif/dir b15 read b14 n.c. b13 complim b12 enable b11 dgnd b10 dgnd b9 dgnd b8 dgnd b7 dgnd b6 dgnd b5 dgnd b4 eoc b3 ovrflw b2 b1b msb b1(msb) 2.2f c11 0.1f c20 u4 9 8 7 6 5 4 3 2 11 1 19 18 17 16 15 14 13 12 0 20 1 74hct573 0.1f c15 33pf c10 1 2 0.1f c18 0.1f c3 2.2f c1 2.2f c14 2.2f c2 2.2f c9 sg8 sg7 2.2f c12 2.2f c21 r2 r1 3.3k r3 1 2 u1 2 3 1 6 5 4 74hct74 sg9 sg6 2.2f c4 20mh l4 ar1 2 3 4 6 7 0.1f c5 20mh l3 u3 9 8 7 6 5 4 3 2 11 1 19 18 17 16 15 14 13 12 0 20 1 74hct573 sg4 sg3 x1 1 7 8 14 2mhz sg2 74hc86 c6 2.2f 20mh l2 0.1f c19 j5 p2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 50 r6 sg5 12 13 11 74hc86 u5 4 5 6 j2 20mh l1 74hc86 b2 2 j3 0.1f c16 0.1f c17 2.2f c7 b1 1 j4 j1 0.1f c8 sg1 b3 comp enable +5va +5va +5va +5va +5va +5va +5va +5vf +5vf +5vf +5vf +5vf +5vf +5vf fif fif rd rd start convert b2 ab9 ab9 +15v +15v eoc ab8 ab8 ab1 ab1 ab2 ab2 ab3 ab3 ab4 ab4 ab5 ab5 ab6 ab6 ab7 ab7 ab16 ab16 ab15 ab15 ab14 ab14 ab13 ab13 ab12 ab12 ab11 ab11 0 1 b a0 1 b a ab10 fifo/dir read complim b15 b14 fst2 ovrflw b1 +5vd +5vd +5vd +5vd +5vd +5vd b4 b5 b6 b7 b1b msb b13 b16 b8 b12 b11 b10 b9 C15v C15v agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd C5va C5va C5va C5va C5va C5va C5va dgnd n d dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd start convert analog input option amplifier 321 7 14 7 (lsb) gain adjust offset adjust 321 1 1 (msb) (lsb) 14 +5vf +5vf comp ads-932 evaluation board 20k r5 1 2 3 +5va C5va u5 2 3 1 u5 9 8 10 74hc86 fst1 u5 32 32 32 1 dgnd 0.1f 0.1f agnd msb ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 7 of 9
comp. binary unipolar scale input range 0 to 0 to C5.5v input range 2.75v bipolar scale msb lsb msb lsb msb lsb msb lsb Cfs +1 lsb C5.499916 1111 1111 1111 1111 0000 0000 0000 0000 0111 1111 1111 1111 1000 0000 0000 0000 +2.749916 +fs C1 lsb Cfs +1 1/2 lsb C5.499874 lsb "1" to "0" lsb "0" to "1" lsb "1" to "0" lsb "0" to "1" +2.749874 +fs C1 1/2 lsb C7/8 fs C4.812500 1110 0000 0000 0000 0001 1111 1111 1111 0110 0000 0000 0000 1001 1111 1111 1111 +2.062500 +3/4 fs C3/4 fs C4.125000 1100 0000 0000 0000 0011 1111 1111 1111 0100 0000 0000 0000 1011 1111 1111 1111 +1.375000 +1/2 fs C1/2fs C2.750000 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0.000000 0 C1/2fs C1/2lsb C2.749958 0111 1111 1111 1111 1000 000 000 0000 1111 1111 1111 1111 0000 0000 0000 0000 C0.000084 C1/2 lsb C1/4fs C1.375000 0100 0000 0000 0000 1011 1111 1111 1111 1100 0000 0000 0000 0011 1111 1111 1111 C1.375000 C1/2 fs C1/8fs C0.687500 0010 0000 0000 0000 1101 1111 1111 1111 1010 0000 0000 0000 0101 1111 1111 1111 C2.062500 C3/4 fs C1 lsb C0.000084 0000 0000 0000 0001 1111 1111 1111 1110 1000 0000 0000 0001 0111 1111 1111 1110 C2.749916 Cfs +1 lsb C1/2lsb C0.000042 lsb "0" to "1" lsb "1" to "0" lsb "0" to "1" lsb "1" to "0" C2.749958 Cfs + 1/2 lsb 0 0.000000 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 C2.750000 Cfs offset binary comp. two's comp. two's comp. table 2b. output coding table 3. input connections input range input pin tie together 0 to C5.5v pin 3 pin 1 to pin 2 2.75v pin 3 pin 2 is no connect figure 6. ads-932 histogram and differential nonlinearity 0.74 dnl (lsb's) C0.56 0 codes 0 digital output code number of occurrences 65,536 65,536 figure 7. ads-932 grounded input histogram this histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ads-932. 0 4410 digital output code 4000 3000 2000 1000 ads-932 16-bit, 2 mhz sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 01 apr 2011 mda_ads-932.b02 page 8 of 9
mechanical dimensions - inches (mm) ordering information model number operating temp. range accessories ADS-932MC 0 to +70c ads-b932 evaluation board (without ads-932) ads-932mm C55 to +125c hs-40 heat sink for all ads-932 models receptacles for pc board mounting can be ordered through amp, inc., part # 3-331272-8 (component lead socket), 40 required. for mil-std-883 product, or surface mount packaging, contact datel. pin 1 index ( on top) 2.12/2.07 (53.85/52.58) 0.018 0.002 (0.457) 0.100 typ. (2.540) 0.110/0.090 (2.794/2.286) seating plane 0.035/0.015 (0.889/0.381) 0.200/0.175 (5.080/4.445) 0.245 max. (6.223) 0.210 max. (5.334) 0.045/0.035 (1.143/0.889) 1.11/1.08 (28.20/27.43) 120 21 40 1.900 0.008 (48.260) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.015/0.009 (0.381/0.229) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286 ads-932 16-bit, 2 mhz sampling a/d converters . makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to change without notice. www.datel.com ? e-mail: help@datel.com ?? datel 11 cabot boulevard, mans? eld, ma 02048-1151 usa itar and iso 9001/14001 registered 01 apr 2011 mda_ads-932.b02 page 9 of 9
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